The present invention is directed generally to data processing systems, and in particular to a processor unit having one portion of the logic circuitry clocked at one clock frequency, and another clocked at a different clock frequency.
Many, if not all, processor units in use today are synchronous machines in that operations are performed in synchronous fashion, to the tune of a periodic clock signal ("clock"). Thus, for example, instructions are executed, data transferred, signals generated, in response to transitions from one level to another of the clock.
Typically, all portions of a synchronous processor unit are operated at the same clock speed. However, it is well known that certain processor operations occur much more frequently than other processor operations; in fact, it has been established that as much as 95% of the more frequently occurring operations are often performed, for example, in about 50% of the logic circuitry making up the processor unit. Thus, operation of the processor unit can be enhanced by running that section of the circuitry performing the majority of processor operations with a faster clock, while operating the remainder of the logic circuitry with a slower clock. This allows the slower-run section to be run in a manner that consumes less electrical power, emits less electrical noise, generates less thermal power, necessitating less heat sinking capability, and can be implemented in less expensive technology, and fabricated in less semiconductor area. At the same time, the overall processor speed (i.e., work throughput) is increased.